高西

真是好孩子日记这么规整

我是愤怒！

说我是好孩子的人貌似就曾经有过一两个

我是愤怒！

三天的假期，却感觉如此漫长。
跑跑升到彩手，斗地主升到地主，基本会用了max和matlab 写了英语作业，这大概就是三天的收获吧
还有，就是恢复了系统，电脑快了些，应用软件也照样好用，不错。
三天，没有做米饭，除了面条就是煎饺子，很是不愿意做饭了，不知道做什么，混一顿算一顿吧。
市内的两家大超市合并了，家电便宜了很多，但可以直接忽略。
而其中一家市特产的牛奶，原来很便宜，现在却消失了，导致只能买基本贵一倍的其他牛奶。
十月了，国内的国庆也完了，我也准备好期中考试了，焦急期盼中～～

看看你

可以回复你了
定期来看看你～～

高西

原帖由 我是愤怒！ 于 2008-10-5 22:27 发表
说我是好孩子的人貌似就曾经有过一两个

不会吧。。。

我是愤怒！

那好好看，要用心看～

我是愤怒！

通信工程有作业了，明天写一下，还有英语的作业，突然多了。
今天认识了专门帮助我的韩国人，周三准备一起吃个午饭。
不过我都开始定回家的飞机票了，才出现这种项目，比较无语，聊胜于无吧，终究不是坏消息。
预计22号的票，希望如此了。

我是愤怒！

报告备份

#include <iostream>
using namespace std;
double POWER;
const double R1=26.9;
const double R2=53.8;
const double R3=134.2;
const double Vrms= 220;
signed int select;
double function_off()
{ return POWER=0;
};

double function_weak(double p,double vrms, double r1, double r2)
{ p=vrms*vrms/(r1+r2);
return p;
};

double function_normal(double p,double vrms,double r2)
{ p=vrms*vrms/r2;
return p;
};

double function_strong(double p,double vrms, double r1, double r2,double r3)
{p=vrms*vrms/((r1+r3)*r2/(r1+r2+r3));
return p;
};


int main()
{ while(select!=4)
{cout<<" Select the switch"<<endl;
  cout<<" 0. off  1. weak  2. normal  3. strong  4. close"<<endl;
cin>>select;

switch(select)
{case 0:
     cout<<"The switch is off and the power is"<<" "<<function_off()<<"w"<<endl<<endl; break;
case 1:
         cout<<"The wind is weak and the power is"<<" "<<function_weak(POWER,Vrms,R1,R2)<<"w."<<endl<<endl; break;
case 2:
         cout<<"The wind is normal and the power is"<<" "<<function_normal(POWER,Vrms,R2)<<"w."<<endl<<endl;; break;
case 3:
         cout<<"The wind is strong and the power is"<<" "<<function_strong(POWER,Vrms,R1,R2,R3)<<"w."<<endl<<endl; break;
case 4:
         cout<<"You have closed the hiredrier."<<endl<<endl; break;
default:
         cout<<"The range or select is from 0 to 4"<<endl<<endl; break;
}
}
}

电路图

[ 本帖最后由 我是愤怒！ 于 2008-10-12 15:32 编辑 ]

我是愤怒！

报告备份
P2-24
A)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY four_input_and_gate is
port( w,x,y,z: in std_logic;
f: out std_logic);
end four_input_and_gate;

architecture dataflow of four_input_and_gate is

signal p: std_logic_vector(1 downto 0);
begin p(0)<=w and x;
p(1)<=p(0) and y;
f<=p(1) and z;
end dataflow;




B)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY four_input_nand_gate is
port( w,x,y,z: in std_logic;
f: out std_logic);
end four_input_nand_gate;

architecture dataflow of four_input_nand_gate is

signal p: std_logic_vector(2 downto 0);
begin p(0)<=w and x;
p(1)<=p(0) and y;
p(2)<=p(1) and z;
f<=not p(2);

end dataflow;

C)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY four_input_nor_gate is
port( w,x,y,z: in std_logic;
f: out std_logic);
end entity;

architecture dataflow of four_input_nor_gate is

signal p: std_logic_vector(2 downto 0);
begin p(0)<=w or x;
p(1)<=p(0) or y;
p(2)<=p(1) or z;
f<=not p(2);
end dataflow;

D)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY four_input_xor_gate is
port( w,x,y,z: in std_logic;
f: out std_logic);
end entity;

architecture dataflow of four_input_xor_gate is

signal p: std_logic_vector(1 downto 0);
begin p(0)<=w xor x;
p(1)<=p(0) xor y;
f<=p(1) xor z;

end dataflow;

E)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY four_input_xnor_gate is
port( w,x,y,z: in std_logic;
f: out std_logic);
end entity;

architecture dataflow of four_input_xnor_gate is

signal p: std_logic_vector(1 downto 0);
begin p(0)<=w xnor x;
p(1)<=p(0) xnor y;
f<=p(1) xnor z;

end dataflow;

F)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY five_input_xor_gate is
port( five_input: in std_logic_vector(4 downto 0);
f: out std_logic);
end entity;

architecture dataflow of five_input_xor_gate is

signal p: std_logic_vector(2 downto 0);
begin
p(0)<=five_input(0) xor five_input(1);
p(1)<=p(0) xor five_input(2);
p(2)<=p(1) xor five_input(3);
f<=p(2) xor five_input(4);

end dataflow;

G)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY five_input_xnor_gate is
port( five_input: in std_logic_vector(4 downto 0);
f: out std_logic);
end entity;

architecture dataflow of five_input_xnor_gate is

signal p: std_logic_vector(2 downto 0);
begin
p(0)<=five_input(0) xnor five_input(1);
p(1)<=p(0) xnor five_input(2);
p(2)<=p(1) xnor five_input(3);
f<=p(2) xnor five_input(4);

end dataflow;

P3_35
A)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity func is
port(s: in std_logic_vector(2 downto 0);
f: out std_logic
);
end func;

architecture behavior of func is

begin
process(s)
begin
case s is
when"000" => f<='1';
when"001" => f<='1';
when "011"=> f<='1';
when others => f<='0';
end case;
end process;
end behavior;

B)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity func is
port(s: in std_logic_vector(3 downto 0);
f: out std_logic
);
end func;

architecture behavior of func is

begin
process(s)
begin
case s is
when"0000" => f<='1';
when"0001" => f<='1';
when "0011"=> f<='1';
when others => f<='0';
end case;
end process;
end behavior;

P4_34
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity multiplier is
port(m: in std_logic_vector(3 downto 0);
q: in std_logic_vector(3 downto 0);
p: out std_logic_vector(7 downto 0));
end multiplier;

architecture behavior of multiplier is
signal s1: std_logic_vector(3 downto 0);
signal s2: std_logic_vector(4 downto 0);
signal s3: std_logic_vector(5 downto 0);
signal s4: std_logic_vector(6 downto 0);
begin
s1<=m when q(0)='1' else "0000";
s2<=m&'0'when q(1)='1' else "00000";
s3<=m&'0'&'0'when q(2)='1' else "000000";
s4<=m&'0'&'0'&'0'when q(3)='1' else "0000000";
p<=s1+s2+s3+s4;

end behavior;

P4_35
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity shifter is
port
(s: in std_logic_vector(1 downto 0);
four_in: in std_logic_vector(3 downto 0);
four_out: out std_logic_vector(3 downto 0)
);
end shifter;

architecture behavior of shifter is
begin
process(s,four_in)
begin
case s is
when "00"=> four_out<=four_in;
when "01"=> four_out<=four_in(0)&four_in(3 downto 1);
when "10"=> four_out<=four_in(1)&four_in(0)&four_in(3 downto 2);
when others=> four_out<=four_in(2)&four_in(1)&four_in(0)&four_in(3);
end case;
end process;
end behavior;

我是愤怒！

期中了，忙了很多。
发现周末总是起不来，吃得也是得过且过，吃饱就好了，反正也是过的糊里糊涂。
飞机票还没定完，不过也应该没什么意外了。
下个礼拜考试，过了下个礼拜，就算是过完了期中了。
不知道什么时候开始，喜怒哀乐已经变的不那么明显了，这一年还没过完，就感觉变了很多。
不过一切都在向好的方向发展～～